RS(n,k) Encoder based on LFCS

Authors

  • Cecilia Sandoval-Ruiz Universidad Nacional Experimental Politécnica de la Fuerza Armada Bolivariana

Keywords:

LFCS, reed solomon encoder, concurrent design

Abstract


This article presents the design of a Reed Solomon encoder circuit based on a concurrent LFCS -Linear Structure Concurrent Feedback-allowing the generation of code redundancy symbols in parallel, provided that you supply the k information symbols to encode simultaneously, the encoder provides at its output corresponding redundancy symbols. To achieve this development was generalized mathematical model describing the behavior of the encoder, the configuration was done in VHDL hardware description language of a Reed Solomon encoder, taking as case study the RS (7.3), the design was simulated validating the proposed operation, and finally the comparison of the encoder implementation between the sequential version and the version based on LFCS, obtaining a reduction of hardware components and optimizing the speed of response and power consumption. In conclusion, the proposed encoder design validates the concurrent model generalized from the correspondence with the architecture of LFCS.

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References

C. Sandoval, A. Fedón, “Codificador y decodificador digital Reed-Solomon programados para hardware reconÆ gurableî. Revista Ingeniería y Universidad. Vol. 11. 2007. pp. 17-31.

C. Hsie, B. Shung, L. Chen. “A Reed-Solomon Product-Code (RS-PC) Decoder Chip for DVD Applications” . IEEE Journal of Solid-State Circuits. Vol. 36. N°. 2. pp. 229-238. 2001. Available in: http:// www.si2lab.org/publications/jnl/hcchang_jssc_01. pdf. Consultada el 23 de enero de 2011.

C. Chang, A. Hyo, L. “High-Throughput LowComplexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems”. IEICE TRANSACTIONS on Communications. Vol. E94-B. 2011. pp.1332-1338. Available in: http:// soc.inha.ac.kr/images/High-Throughput_LowComplexity_Four-Parallel_Reed-Solomon_Decoder_ IEICE%282011.05.01%29_published.pdf. Consultada el 05 de abril de 2011.

L. Hanho. “High-speed VLSI architecture for parallel Reed-Solomon decoder”. IEEE Trans. Very Large Scale Integr. Syst. Vol. 11. 2003. pp. 288-294. Available from: http://soc.inha.ac.kr/images/Itvlsi03_lee.pdf. Consultada 10 de noviembre de 2010.

P. Sobe. Parallel Reed/Solomon Coding on Multicore Processors. In Proceedings of the 2010 International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI ë10). IEEE Computer Society. Washington DC, USA. 2010. pp. 71-80, Available from: http://storageconference.org/2010/Papers/ SNAPI/8.Sobe.pdf. Consultada 11 de agosto de 2011.

C. Sandoval. “Multiplicador Paralelo en Campos Finitos de Galois GF (2m) Aplicado a Códigos Reed Solomon con longitud ajustable sobre FPGA”. Congreso Internacional de Investigación UC. Vol. 1. 2010. pp. 42-48.

Published

2012-10-03

How to Cite

Sandoval-Ruiz, C. (2012). RS(n,k) Encoder based on LFCS. Revista Facultad De Ingeniería Universidad De Antioquia, (64), 68–78. Retrieved from https://revistas.udea.edu.co/index.php/ingenieria/article/view/13116