Efficient hardware implementation of a full COFDM processor with robust channel equalization and reduced power consumption
DOI:
https://doi.org/10.17533/udea.redin.17040Keywords:
OFDM, field programmable gate arrays (FPGAs), radio frequency, receivers, channel coding, channel estimationAbstract
This work presents the design of a 12 Mb/s Coded Orthogonal Frequency Division Multiplexing (COFDM) baseband processor for the standard IEEE 802.11a. The COFDM baseband processor was designed by using ourdesigned circuits for carrier phase correction, symbol timing synchronization, robust channel equalization and Viterbi decoding. These circuits are flexible, parameterized and described by using generic structural VHDL. The COFDM processor has two clock domains for reducing power consumption, it was synthesized on a Stratix II FPGA, and it was experimentally tested by using 2.4 GHz Radio Frequency (RF) circuitry.
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