Efficient hardware implementation of a full COFDM processor with robust channel equalization and reduced power consumption

  • Alexander López-Parrado Universidad del Valle https://orcid.org/0000-0002-0274-6901
  • Jaime Velasco-Medina Universidad del Valle
  • Julián Adolfo Ramírez-Gutiérrez CEIFI

Abstract

This work presents the design of a 12 Mb/s Coded Orthogonal Frequency Division Multiplexing (COFDM) baseband processor for the standard IEEE 802.11a. The COFDM baseband processor was designed by using ourdesigned circuits for carrier phase correction, symbol timing synchronization, robust channel equalization and Viterbi decoding. These circuits are flexible, parameterized and described by using generic structural VHDL. The COFDM processor has two clock domains for reducing power consumption, it was synthesized on a Stratix II FPGA, and it was experimentally tested by using 2.4 GHz Radio Frequency (RF) circuitry.
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Published
2013-10-18
How to Cite
López-Parrado A., Velasco-Medina J., & Ramírez-Gutiérrez J. A. (2013). Efficient hardware implementation of a full COFDM processor with robust channel equalization and reduced power consumption. Revista Facultad De Ingeniería Universidad De Antioquia, (68), 48-60. Retrieved from https://revistas.udea.edu.co/index.php/ingenieria/article/view/17040